A common problem with switching power supplies is the "unstable" switching waveform. Sometimes, the waveform jitter is obvious, and noise can be heard from the magnetic element. If the problem is related to printed circuit board (PCB) layout, it can be difficult to determine the cause. EMC is also very focused on (PCB) layout, which is why it is crucial to correctly lay out PCBS early in the design of switching power supplies. Its importance cannot be overstated.

A good layout design optimizes power efficiency, reduces thermal stress and, most importantly, minimizes noise and the interaction between wiring and components. To achieve these goals, it is important that designers understand the current conduction paths and signal flows in switching power supplies. The following discussion presents design considerations for the correct layout design of non-isolated switching power supplies.

Layout:

For embedded DC /DC power supplies on large system boards, the power output should be located near the load device to minimize the interconnect impedance and conducted voltage drop across the system. PCB wiring enables optimal voltage regulation, load transient response, and system efficiency.

In addition, large passive components (such as inductors and electrolytic capacitors) should not block air flow to low-profile, surface-mount semiconductor components (such as power MOSFETs, PWM controllers, etc.). To prevent switching noise from disrupting other analog signal systems in the switch, avoid routing sensitive signals below the power supply as much as possible. Otherwise, it is necessary to use an internal ground layer between the power layer and the small signal layer for shielding.

It should be noted that this power supply location and board space planning should be done in the early design/planning stage of the system. Unfortunately, sometimes people focus first on other, more "important" or "exciting" circuits on a large system board. If power management/power supply is the last consideration and relegated to the space left on the board, then that certainly doesn't help ensure an efficient and reliable power supply design.

Placement of layers

On multilayer PCB boards, it is very necessary to place the DC ground layer or DC input or output voltage layer between the high-current power component layer and the sensitive small-signal routing layer. The ground layer and/or DC voltage layer provides AC ground to shield small signal wiring from noisy power supply wiring and power supply components.

In general, the ground or DC voltage plane of a multilayer PCB should not be segmented. If segmentation cannot be avoided, the number and length of traces in these planes must be minimized. The direction of the wire should be the same as the flow of the large current to minimize the impact.

Figures 1a and 1c provide examples of undesired layer arrangements for 6 - and 4-layer PCBS for switching power supplies. In these examples, the small signal layer is sandwiched between the high-current power supply layer and the ground layer. These configurations increase capacitive noise coupling between the high current/voltage power layer and the small analog signal layer. To minimize noise coupling, Figures 1b and 1d give an example of the layer arrangement required for a 4 - and 6-layer PCB design.

Figure 1. Desired and undesirable layer arrangements for 6-layer and 4-layer PCBS

In both examples, the small signal layer is shielded by the ground layer. It is important to always place a ground layer next to the external power stage layer. Finally, it is also desirable to use thick copper in the external high-current power supply layer to minimize the conduction loss and thermal resistance of the PCB.

Power level component layout

Switching power supply circuit can be divided into power level circuit and small signal control circuit. Power level circuits include components that conduct large currents. Typically, these components should be placed first. The small signal control circuit is then placed at a specific location in the layout.

Inductance High current routes should be short and wide to minimize PCB inductance, resistance, and voltage drop. This is especially important for tracks with high di/dt pulsating currents.

The solid line represents the continuous current path, and the dashed line represents the pulsating (switching) current path. The pulsating current path consists of the wiring connected to the input decoupled ceramic capacitor CHF, the top controlling FETQT, and the bottom synchronizing FETQB with its optional parallel Schottky diode.

Figure 2a shows the parasitic PCB inductance in these high di/dt current paths. Due to parasitic inductance, the pulsating current path not only radiates the magnetic field, but also creates high voltage ringing and spikes on the PCB track and MOSFETs. In order to minimize the inductance of the PCB, the pulsating current loop (thermal loop) should be arranged so that it has a minimum perimeter and consists of short and wide tracks.

Figure 2. Minimizing the high di/dt loop area in a synchronous buck converter. (a) High di /dt loops (hot loops) and their parasitic PCB inductors, and (b) layout examples.

The high-frequency decoupling capacitor CHF should be an X5R or X7R dielectric ceramic capacitor from 0.1µF to 10µF with very low ESL and ESR. Higher capacitance dielectrics, such as Y5V, can significantly reduce capacitance across voltage and temperature ranges. Therefore, for CHF, these types of capacitors are not preferred.

Figure 2b provides an example of the layout of a critical pulsating current loop (thermal loop) in a buck converter. In order to limit the resistance voltage drop and the number of through-holes, the power components should be placed on the same side of the board and routed in the same layer. When you need to route the power supply to another layer, select a route in the continuous current path. When using through-holes to connect PCB layers in a high-current loop, multiple through-holes should be used to minimize through-hole impedance.

Similarly, Figure 3 shows continuous and pulsating current loops (thermal loops) in a boost converter. In this case, the high-frequency ceramic capacitor C HF should be placed near the output side of the MOSFET QB and the boost diode D.

Figure 3. Continuous and pulsating current path of the Boost converter

The loop consisting of a switch QB, a rectifier diode D, and a high-frequency output capacitor CHF must be minimized. Figure 4 shows an example of the layout of a pulsating current loop in a boost converter.

Figure 4. Minimizing the high di/dt loop area in the Boost converter. (a) High di/dt loops (hot loops) and their parasitic PCB inductors, and (b) layout examples

Isolate and minimize high dv/dt switching areas

In Figures 2 and 4, the SW node voltage oscillates between VIN (or VOUT) and ground at a high dv/dt rate. This node is rich in high-frequency noise components and is a powerful source of EMI noise. In order to minimize the coupling capacitance between the SW node and other noise sensitive tracks, the SW copper area should be minimized.

However, on the other hand, in order to conduct high inductive currents and provide heat sinks for the power MOSFETs, the PCB area of the SW node cannot be too small. It is usually best to place a ground copper area below this SW node to provide additional shielding.

Sufficient copper area to limit thermal stress on power components

In designs without an external heat sink for surface-mounted power MOSFETs and inductors, there must be sufficient copper area to act as a heat sink. For DC voltage nodes, such as input/output voltage and power grounding, it is desirable to make the copper area as large as possible.

Multiple through-holes help to further reduce thermal stress. For high dv/dt SW nodes, the appropriate size of the copper area of the SW node is a design trade-off between minimizing noise associated with dv/dt and providing good thermal performance for the MOSFETs.

Correct pad pattern for power components to minimize impedance

It is important to note the pad (or pad) pattern of power components, such as low ESR capacitors, MOSFETs, diodes, and inductors. Figures 8a and 8b show examples of the desired and required power component pad patterns, respectively.

  

Figure 5. Desired and unwanted pad patterns for power components. (a) Improper use of cooling pads for power assembly pads, and (b) recommended pad pattern for power assembly pads.

As shown in Figure 5b, for decoupling capacitors, the positive and negative through holes should be as close to each other as possible to minimize the PCB's effective series inductance (ESL). This is especially effective for capacitors with low ESL. High-value low ESR capacitors are usually more expensive. Improper pad patterns and poor wiring can reduce its performance, thereby increasing the overall cost. Typically, the desired pad pattern reduces PCB noise, reduces thermal impedance, and minimizes the wiring impedance and voltage drop of high-current components.

A common mistake in the layout of high-current power components is the incorrect use of the heat pad pad pattern, as shown in Figure 5a. Unnecessary use of the cooling pad pattern increases the interconnect impedance of the power components. This results in higher power losses and reduces the decoupling effect of low ESR capacitors. If the through-hole is used to conduct a large current, a sufficient number of through-holes must be used to minimize the through-hole impedance. Again, heat dissipation holes should not be applied to these holes.

Separation of input current paths between power sources

Figure 6 shows an application where several on-board switching power supplies share the same input voltage rail. When these power supplies are out of sync with each other, it is necessary to separate the input current routes to avoid the common impedance noise coupling between different power supplies. The requirement that each power supply has a local input decoupling capacitor is less important.

Figure 6. Input current path between separate power supplies

Control circuit layout control circuit

The control circuit should be located away from noisy switching copper wire areas. For buck converters, the control circuit is best near the VOUT + side, and for boost converters, the control circuit is best near the V IN + side, where the power line carries continuous current.

If space permits, place the control IC at a small distance (0.5-1 inches) from noisy and hot power MOSFETs and inductors. However, if space constraints force the controller to be placed close to the power MOSFETs and inductors, extra care must be taken to isolate the control circuit from power components with ground layers or wiring.

Separate control circuits for signal grounding and power grounding shall have separate signal (analog) grounding islands between them and power level grounding. If there are separate signal ground (SGND) and power ground (PGND) pins on the controller IC, they should be wired separately. For a controller IC with an integrated MOSFET driver, the small signal portion of the IC pin should use SGND, as shown in Figure 7.

Figure 7. Decoupling capacitor of controller IC from ground

Only one connection point is required between SGND and PGND. You want to restore SGND to a clean point on the PGND plane. Two ground connections can be made by connecting the two ground cables under the controller IC. Figure 7 shows the preferred ground separation for the chip power supply. In this example, the IC has a bare GND pad. It should be welded to the PCB to minimize electrical and thermal impedance. Multiple through holes should be placed on this GND pad area.

Decoupling capacitor of the controller IC

The decoupling capacitor of the controller IC should be physically close to its pin. In order to minimize the connection impedance, it is best to connect the decoupling capacitor directly to the pin without using a through-hole. As shown in Figure 8, decoupling capacitors for the following chip pins should be placed closely: current detection pin, SENSE + / SENSE -, compensation pin, ITH, signal ground pin, SGND, feedback voltage divider pin, FB, IC VCC voltage pin INTV CC and power ground pin PGND.

Minimize loop area and crosstalk

Separated noise track and sensitive track

Two or more adjacent conductors can be capacitatively coupled. A high dv/dt voltage change on one conductor will couple the current to the other conductor via a parasitic capacitor. In order to reduce noise coupling from the power stage to the control circuit, it is necessary to keep the noise switch track away from the sensitive small signal track. If possible, route noisy and sensitive routes on different layers, and use internal ground layers to shield noise.

Current detection trace and voltage detection trace

Among all small signal traces, current detection traces are the most sensitive to noise. The amplitude of the signal is usually less than 100mV, which is comparable to the noise amplitude. Its SENSE + / Sense-trace should be routed parallel to the minimum interval (Kelvin detection) to minimize the chance of picked up di/DT-related noise, as shown in Figure 8.

Figure 8. Kelvin sensing (a) RSENSE and (b) inductor DCR sensing for electrofluometry

In addition, filter resistors and capacitors for current detection wiring should be placed as close to the IC pin as possible. If the noise is injected into the long detection line, this will provide the most efficient filtering. If the inductor DCR electrofluometry is used with an R/C network, the DCR sensing resistance R should be near the inductor and the DCR sensing capacitance C should be near the IC.

If a pass hole is used in the return path of the wire to SENSE -, that pass hole should not come into contact with another internal VOUT + layer. Otherwise, the hole may conduct a large VOUT + current and the resulting voltage drop may distort the current detection signal. Avoid wiring current detection traces near noisy switching nodes (TG, BG, SW, BOOST traces). If possible, place the ground layer between the electrical trace and the layer with the power level trace.

If the controller IC has differential voltage remote sensing pins, Kelvin sensing connections should also be used to separate the positive and negative wires.

Stitch width selection

Current levels and noise sensitivity are unique to a particular controller pin. Therefore, specific track widths need to be selected for different signals. Typically, small signal networks may be narrow and have 10 to 15 mil wide tracks. High current networks (gate driven, VCC and PGND) should have short and wide routes. It is recommended that these nets be at least 20 mil wide.

Input power surge peak voltage

When the DC-DC circuit is switched on and disconnected from heavy load, it often generates a high peak voltage instantaneously. The method to reduce the peak amplitude is the equivalent series resistance (ESR) of the line impedance and capacitance.

For example, in the LDO circuit, the power is relatively low, and when the higher input is powered on, the resistance is generally 2-10 ohms in series at the positive input extreme.
For example, in DC-DC circuits, the general input capacitor uses an electrolytic capacitor with a higher ESR equivalent series resistance, and the electrolytic capacitor scheme can also be used in LDO circuits.

Circuit PCB design requirements focus

1. The input capacitor CIN is placed near the input Vin pin plate of the chip and the capacitor ground end is placed in the PGND of the power, which increases the pass hole, reduces the impedance, and reduces the presence of parasitic inductance. Because the input current is discontinuous, the noise caused by parasitic inductance will adversely affect the voltage withstand of the chip and the logic unit.

2. The circuit of the power circuit is as short and thick as possible, keeping the loop area small,

3. SW/LX is a noise source that ensures current while keeping the area as small as possible, away from sensitive and easily disturbed locations such as FB output feedback circuits,

4. The output capacitor COUT is placed near the inductor to increase the pass hole and reduce the impedance.

5. The FB feedback resistor is connected to the FB pin as short as possible and placed close to the IC's FB pin to reduce noise coupling,

6. Heat dissipation design, the bottom of the chip as many holes as possible to increase the heat dissipation design

7. The circuit can not go from the bottom of the inductor (interference is large). You can drill a hole in the grounding end of the resistor or capacitor. If it is input capacitor CIN or output capacitor COUT, more holes need to be added. Ensure clean and stable power loop.